This project implements a complete Universal Verification Methodology (UVM) based verification environment for the AMBA AXI protocol. The verification environment is designed to validate AXI read and ...

UVM Verilog VHDL VCS NCSim ModelSim Questa AHB AXI AMBA SRAM Flash DDR memory controllers debugging test planning CC ARM cores SVA microcontroller architectures interconnect protocols testbench ...

Customer stories Events & webinars Ebooks & reports Business insights GitHub Skills ...