This project implements a simplified DDR3 memory controller designed to interface with a 1Gb x8 DDR3 SDRAM device. The controller manages bank state machines, enforces timing constraints, and provides ...

Abstract: Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip designs. Nevertheless, FPGA vendors can not accurately specify ...

Final project repo of ECE551 in Fall 2021 at UW Madison. Owned by Team Doraemon: Shichen (Justin) Qiao, Xin Su, Wenfei Huang, and Kailun Teng. Changed xx and yy in KnightsPhysics.sv to type logic.

When learning to program FPGAs or ASICs using hardware description languages, such as Verilog or VHDL, being able to simulate code is an important part of the learning process. In fact, being able to ...

Abstract: This paper focus on the design of a reconfigurable Linear Feedback Shift Register (LFSR) for Very Large Scale Integration (VLSI) Integrated Circuit (IC) testing. The advancement in VLSI ...