Abstract: We present a Mathematics of Arrays (MoA) and ψ-calculus derivation of the memory-optimal operational normal form for ELLPACK sparse matrix-vector multiplication (SpMV) on GPUs. Under the ...
Abstract: In this paper, a silicon photomultiplier (SiPM) array module is evaluated and implemented as the receiver of laser rangefinding experiments to simultaneously measure the range of multiple ...
We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in ...
Digital beamforming phased arrays are becoming an increasingly common antenna product both for defense and commercial applications. The primary technological advancement making this possible is the ...
This repository includes a pure Vitis HLS implementation of matrix-matrix multiplication (A*B=C) for Xilinx FPGAs, using Xilinx Vitis to instantiate memory and PCIe controllers and interface with the ...
Monolithic arrays of silicon p-n junctions are commonly used to deliver spatial information on impinging radiation, with the advantages of low-noise and fast signal generation. Additionally, array ...
Hardware architectures composed of resistive cross-point device arrays can provide significant power and speed benefits for deep neural network training workloads using stochastic gradient descent ...
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