GitHub

An elementary-level smartnic example, with fpga-based integrated structure.

Assuming a gigabit Ethernet port is used and the interface with the physical layer chip is assumed to be RGMII Above the physical layer is a MAC module Packet from/to the MAC passes through a DMA ...
GitHub

simple spi communication between FPGA and MCU

This repository implements two SPI-based communication methods between FPGA and MCU: ram-like and instruction parsing. Both ways realize the modification of target registers through specific SPI ...
Design-Reuse

Actel's New ARINC 429 IP Core Reduces Cost and Simplifies Integration for Avionics Systems Designers

Immune to Firm Errors, Core429 Bus Interface Offers Full-Channel Configurability and Programmable FIFO Capability MOUNTAIN VIEW, Calif., October 4, 2004 - Underscoring its longstanding position as a ...
EDN

On-Chip Design Verification with Xilinx FPGAs

Xilinx Virtex-II Pro devices have redefined FPGAs. The Virtex-II Pro brings with it not only a denser and faster FPGA, but an IBM PPC 405 core and up to twenty four 3.125Gb/s high speed serial ...
Design-Reuse

Mentor Graphics Unveils Inventra IPX to Accelerate and Ease Intellectual Property Evaluation and Integration for PLD Designs

SAN JOSE, Calif.--(BUSINESS WIRE)--Aug. 27, 2001-- Mentor Graphics Corporation (Nasdaq:MENT) today announced the Inventra(TM) IPX suite of intellectual property (IP) soft cores. Accessed directly ...