Semiconductor Engineering

Observability Is A Missing Layer In AI-Era Chiplet Design

In next-generation silicon, AI can interpret system behavior at scale, but only if observability is designed into the fabric ...
POWER Magazine

Energizing AI: How Modular Substations Alleviate Data Center Power Bottlenecks

Data center developers have mastered server density and cooling, but power interconnection remains stubbornly slow. Modular substations built in factories rather than fields are emerging as the most ...
EDN

CoWoS, wafer-scale and CoWoP: Why AI packaging bottleneck is moving

A basic comparison between CoWoS, wafer-scale integration, and CoWoP establishes distinctions among package substrate, ...
IEEE

High capacity motors on-line diagnosis based on ultra wide band partial discharge detection

Abstract: A noninvasive ultra-wide band (UWB) partial discharge technique was employed in high capacity motors diagnosis. Those motors are installed and operating in an oil pumping plant. The ...
Semiconductor Engineering

Design Customization Puts Heavy Burden On Verification

Experts At The Table: The pressure on verification engineers to ensure a device will function correctly has increased exponentially as chips become more complex and heterogeneous. Semiconductor ...
Hackaday

VexRiscv: A Modular RISC-V Implementation For FPGA

Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU ...